A low-power, low-noise CMOS amplifier for neural recording applications

There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode–tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise–power tradeoff limit—the noise efficiency factor—for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5m CMOS process, passes signals from 0.025 Hz to 7.2 kHz with an input-referred noise of 2.2 Vrms and a power dissipation of 80 W while consuming 0.16 mm of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 W while maintaining a similar noise–power tradeoff.